Oliver Bartels wrote:
IP routing fits ideal with pipelining, as there is no dependence between different IP packets, the first section of the pipeline decodes the first portion of the IP address, then passes the packet header to the next section responsible for the next portion of the address, at this time the first section starts decoding the next packet etc.
It merely means that pipeline clock can be as short as memory clock regardless of the number of memory references. However, as I said
Note that, at 1Tbps, 500B packet is 4ns long, at 10Tbps 0.4ns.
and as there are a lot of shorter packets, we should be able to lookup routing tables for, say, every 1ns or 0.1ns. If we have a 1Tbps port and a pipelined memory with pipeline clock of 200MHz, we need 5 copies of routing tables lnterleaved 5 ways for the port. If we have a router with 10 1Tbps ports, we need 50 copies for the router. So, it's better to have 50 copies of small memory than large memory. Or, can you make already pipelined memory operating at 200MHz 5 or 50 times more faster by 5 or 50 times more stages of pipeline? Note that, if you assume GaAs and/or full custom chips for further performance, please don't forget costs associated for it considering the number of backbone routers. Note also that, if you want to put everything on a chip to increase clock, there is a very hard limit on the routing table size. Masataka Ohta